1. Technical Field
The present invention relates to the chip testing field, in particular to a method for testing a plurality of transistors in a target chip.
2. Description of Related Art
As microelectronic technology evolves, the integrated circuit industry now has entered an ultra-deep submicron phase. The critical dimensions of electronic devices become smaller and smaller and the chips bigger and bigger. Tens of millions of transistors and circuits can be integrated onto a single chip. The current state of the art semiconductor process node is 28 nm. The minimum line width of the corresponding layout becomes smaller and smaller, while the chip scale gets bigger and bigger and complexity higher and higher. At present, the mainstream lithographic technique is 198 nm lithography. During production of system chips, many factors have direct effects on the yield. Those factors include various short-circuit and open-circuit situations in the manufacturing process. It can be seen that, quantization of those factors is very important for improving the yield. Therefore, how to reduce defects in the manufacturing process and improve the yield is a severe problem in front of the semiconductor design and manufacturing company.
At present, methods for improving the yield mainly include:
(1) Optical proximity correction technology: The optical proximity effect is more obvious in the advanced process. The patterns on a wafer generated through a lithography machine are different from the layout practical_layout, thereby causing defects. Thus, before the lithography steps, the patterns on the mask were corrected through optical proximity correction technology, so the finally produced patterns are consistent with the original layout.
(2) Test chip technology: aiming at the problem that any process links of the semiconductor production may cause defects, this technology improves the yield by the following steps: test structures_proceeding tremendous data experiment design through using test structures, designing a test chip layout, manufacturing the test chip, testing this chip, and analyzing the testing data to find out causes of the defects in the process line. The test chip is of course designed to detect the causes of defects in the process line, comprised of a large number of test structures. Two methods for designing the test structures are as follows: (1) designing the parameterized units, and data experiment design; (b) finding out the positions required to be tested in the exiting chip layout.
(3) Design for Manufacturability (DFM): introduce some manufacturing rules in the process of chip design, and consider manufacturability. Reduce system defects to improve the yield.
Among the above three methods, the test chip technology is the most common one. Manufacturing the test chip requires creating test structures. At present, the method adopted in the industrial field is referring to the positions and patterns required to be noted in the product chip layout. Those positions and patterns include factors with effect on the yield that will be researched by users. Then, the test structures and the testing template are generated manually. Finally, the test chip template is electrically tested with instruments.
Generating the test structures manually requires to cut the chip layout_manually or to edit a layout_including areas of the positions required to be tested in a layout editor. A great number of positions with effect on the yield are required to be tested, so generating the test structures manually has the following shortcomings: (1) the product has a great number of positions required to be tested, even thousands, so it costs a lot of time in the manual generation mode; (2) generating the test structures manually is easy to get wrong.
Generating the test chip template manually is to arrange the pads in an array. The test structures are placed among the pads. After manual placement and wiring, the testing machine performs electric testing through the pads. Generating the test chip template manually has the following shortcomings: (1) there are tremendous test structures and may be thousands or tens of thousands, so it costs a lot of time to generate the test chip template through manual placement and wiring; (2) manual placement and wiring are easy to get wrong; (3) the utilization ratio of the area is very low, causing very high testing cost.
In conclusion: it is necessary to invent a new method for generating a test chip layout to solve the mentioned problems.